The use of optical communications promises to significantly enhance computing power. The use of a light based transmission media has significant performance advantages over conventional electrical communications. In order to take advantage of the enhanced rate of data transmission which can be transmitted by light based systems, data link components such as optical receivers and transmitters must process the data to be sent or received at ever increasing data rates. Even though the transmitter or receiver must process the data faster, parts of the transmitter or receiver must also provide increased logical function for a unit of chip area. Therefore, the data link in optical communications must not only process data faster but it must also have increased functional capability. The requirement of increased performance is typically met by implementing some functions of the data link in a differential current switch (DCS) family of circuits. This is because the DCS family of circuits offers increased speed and better rejection of power supply noise than other circuit families. The requirement of increased functional capability is typically met by implementing some functions of the data link in a super buffer logic (SBL) or direct coupled logic (DCFL) family. This is because the SBL or DCFL family of circuits offer a compact and flexible design capability with low power dissipation.
The DCS family of circuits combines a gain stage with a push-pull output stage in order to create a logical block which has high power supply noise rejection and uses a power supply which is common to other circuit families. The DCS designs have a 0.7 volt signal swing referenced to the applicable power supply, here a 3.6 volt CMOS compatible supply. As a result of this design base, the DCS family of circuits is very efficient in terms of active device area and performance for implementing certain types of functions, such as, latches, exclusive ORs, and multiplexers among others. This same design base makes the DCS family inefficient at implementing other functions such as multiple input ANDs, or NORs. However, the SBL family of circuits uses an active load to reduce the propagation delay of the circuits while maintaining a minimum number of devices for any logical function. The SBL designs also have a 0.7 volt signal swing but it is reference to ground (0 volts). This design base makes SBL efficient at implementing ANDs and NORs but inefficient at implementing latches and multiplexers. The data link requires both types of functions. As a result, it would be desirable to combine both types of circuits in a single design. The problem with this is that the input/output voltage levels of the DCS circuit family do not match the input/output voltage levels of the SBL circuit family. This means that the two families of circuits cannot directly send data to each other.